Palani platform · AI inference
Compute near data · Efficient inference
Silicon milestone · Tapeout achieved
Execution path · Silicon to deployment
Protected architecture · Shared selectively
Partnership path · Validation and productization
Palani platform · AI inference
Compute near data · Efficient inference
Silicon milestone · Tapeout achieved
Execution path · Silicon to deployment
Protected architecture · Shared selectively
Partnership path · Validation and productization
Palani AI compute platform
Efficient AI inference needs a new compute path.
optoML is building Palani, a hybrid analog-digital AI compute platform that brings compute near data for efficient inference across edge devices, industrial sensing systems and scalable infrastructure.
Palani product view
A hybrid compute path where efficient dataflow, control and deployment come together from edge systems to scalable inference infrastructure.
Live platform map
Inputs
vision and sensor streams
Software
model mapping and control
Inference
classification and insight
Systems
factory, field and scale
Compute near dataReduce avoidable movement
Platform stackSilicon to deployment
Scale pathEdge to infrastructure
Why optoML
The bottleneck is no longer only compute.
In many AI systems, a large share of energy is spent moving data rather than doing arithmetic. Palani is designed around compute near data, reducing avoidable movement across the inference path.
Conventional separation
Memory and compute sit apart, so data travels repeatedly across the system.
Palani direction
Bring compute closer to data to improve inference efficiency and responsiveness.
Why this matters
In many inference systems, a major share of energy can be dissipated in moving data across the system rather than doing the arithmetic itself. Palani is built to attack that imbalance.
Data movementEnergy spent shifting activations and weights across the memory and compute path.
Arithmetic and controlThe remaining share covers actual compute, orchestration and other system activity.
Public illustrative view. Exact split varies by model, memory hierarchy and system configuration.
Palani design response
Palani uses a hybrid analog digital compute approach. Analog is used where energy efficiency and data movement matter most. Digital is used where control, precision, programmability and system coordination are critical.
Analog advantage
Efficient matrix style computation closer to the dataflow.
Digital strength
Control, calibration, precision handling and software driven execution.
Less movement
Reduce unnecessary trips between memory and compute.
More responsive systems
Support real time decisions in cameras, machines and field devices.
Consistent deployment roadmap
Use one compute platform across edge, fusion and infrastructure classes.
Key updates
Execution signals for investors and customers.
A public-safe update block that shows momentum without exposing full team details, proprietary implementation or unvalidated performance claims.
TSMC 12nm FinFET tapeout
First FinFET test chip taped out in 11 months, demonstrating advanced-node system-on-chip execution capability.
Kaynes Semicon MoU signed
MoU signed for packaging, post-silicon validation, OSAT and system readiness path in India.
$1.8M pre-Series A raised
Pre-Series A funding raised from Bluehill and A99 to support productization, pilots and next-stage silicon execution.
Detailed performance claims and benchmark data can stay inside the private investor deck under NDA.
Architecture
A clear architecture story for efficient AI inference.
Palani combines analog efficiency, digital control, interfaces and software enablement in one protected platform architecture.
Hybrid analog digital compute fabricAnalog where energy and data movement matter, digital where control, precision and programmability matter.
Digital control planeScheduling, orchestration, model execution, calibration and system coordination.
System interfacesBoard, memory and deployment integration paths for real products.
Software enablementModel mapping and application deployment as part of the platform.
Applications
Built for places where inference has to be local, fast and efficient.
Each application block is intentionally short, visual and easy to scan.
Industrial AI vision
Inspection and verification at line speed.
Sensor fusion
Vision, radar and signals fused locally.
Industrial automation
Embedded AI for smart production cells.
Sovereign edge AI systems
Local intelligence for connected infrastructure, industrial sites and secure field environments.
Scalable inference systems
A longer range path for efficient inference beyond a single edge device.
Execution
From silicon proof to package, board and deployment readiness.
The public narrative should show credible semiconductor execution while keeping detailed architecture, benchmarks and customer specifics in the private deck.
01
130nm proof-of-concept completed
Early silicon foundation established before moving into advanced-node system-on-chip execution.
02
12nm FinFET test chip taped out
Advanced-node test chip taped out in 11 months, validating the team execution model.
03
Packaging and post-silicon path
Kaynes Semicon MoU supports packaging, post-silicon validation, OSAT and system readiness.
04
Funded productization path
$1.8M pre-Series A from Bluehill and A99 supports pilots, productization and next-stage execution.
